This invention relates to systems for measuring, comparing or synchronizing the time differences between a pair of pulses in a pair of pulse trains or alternatively generating a pulse train in timed relationship to a given pulse train.
More particularly, this invention is shown in various embodiments having applications for measuring the time differential between pulses in a pair of pulse trains, means for providing timing signals to individual circuits at various locations within a computer, a self-adjusting delay or phase equalizing means and a frequency dependent demodulating system. The embodiments show both an analog and digital basis for operation.
The prior art known to applicant shows numerous systems involving phase locked loops. The present invention differs from a phase locked loop in that the phase locked loop is responsive to an entire pulse or the width of the pulse while the present invention responds only to the leading or, selectively, the trailing edge of a pulse. Similarly, some prior art patents show voltage generating devices based on the phase locked loop for controlling such devices as a voltage controlled oscillator. One such patent is U.S. Pat. No. 4,142,158. This patent does not anticipate the present invention, however, because the present invention does not use a voltage controlled oscillator nor a phase locked loop of the type shown in the patent. However, the art field is related because the type of problems typically solved by phase locked loops relate to the applications for the present invention. U.S. Pat. No. 4,105,932 shows a phase locked loop and a voltage controlled oscillator for the measurement purpose of generating clock signals for the calibration of an oscilloscope. However, the present invention is dissimilar from that patent. Other related patents showing phase locked loops and voltage controlled oscillators are U.S. Pat. Nos. 4,065,796 and 4,055,814. U.S. Pat. No. 4,051,440 shows a phase locked loop in a demodulator circuit.
The most relevant prior art known to applicant is believed to be U.S. Pat. No. 4,137,503 which shows a system for varying a time delay in a clock signal by a time determined by a voltage controlled phase correction input. However, the invention shown in that patent does not provide for phase comparison or correction in the way provided by the present invention. The present invention provides a feedback loop which is not found in the patent. Advantages of the present invention over the device shown in the patent can clearly be found in the way the devices operate. The patented invention in response to a frequency variation or drift will cause a phase detector to produce a correction signal causing a change in the delay signal but this correction will be erroneous and produce an incorrect correction. Thus, the circuit shown in the patent will be sensitive to frequency variations in a way which will not occur with the present invention.
In general, the prior art devices for performing functions similar to the applications of the present invention involve phase locked loops which are sensitive to pulse width. Such devices often respond inappropriately to changes in frequency or to changes in pulse width where the operation of the device is not intended to change in response to pulse width or in response to changes in frequency. The present invention provides a system which does not have an undesirable response to changes in frequency or to changes in pulse width. The delay lock loop of the present invention is not a true phase locked loop type of circuit. Because of the present invention's use of either leading or trailing edge transitions on pulses, it is believed that the present invention of a delay lock loop has a separate standing in the art from that of the phase locked loop. It is believed, however, that the phase locked loop art is relevant because the applications are similar to that of the present invention.